The present disclosure relates generally to the fabrication of semiconductor devices, and more particularly, to a method and process for depositing a silicon germanium alloy onto a semiconductor substrate.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 um and even 90 nm feature sizes.
Bipolar transistors are important components in, for example, logic circuits, communications systems, and microwave devices. A bipolar transistor is essentially a three terminal device having three regions, an emitter, base and collector region, wherein the emitter and collector regions are of one conductivity type and the base is of another.
Since the advent of bipolar transistors, many attempts have been made to improve the performance of the transistor. However, as device characteristics have decreased and speed and performance requirements have increased, the composition of the different portions of the bipolar transistor become critical.
For example, in one type of heterojunction transistor, the transistor is formed with a silicon collector region, a base region composed of a silicon-germanium (SiGe) alloy, and a silicon emitter region. The mixed crystal semiconductor base layer may have a uniform distribution of germanium in silicon or may contain a graded distribution of germanium in the silicon. The graded SiGe distribution is often provided in order to increase the bandgap of the transistor. With the above described structure of a wide bandgap transistor and the fact that germanium has a large electron mobility, performance of the transistor is enhanced.
However, a problem often occurs during deposition of the SiGe base layer. Specifically, discontinuities begin to appear when SiGe is deposited between a combination of silicon, oxide, and poly films, expecially on shallow trench isolation (STI) oxide. The discontinuities appear as gaps in the SiGe layer on STI oxide, which causes poor poly sheet resistance for connection with the base electrode.
This problem is exacerbated by further attempts to improve heterojunction bipolar transistor performance, such as decreasing the width of the base region of a transistor and decreasing the base transit time for a constant base width. Also, it is important not to adjust any processing requirements which may introduce defects into the single-crystal substrate or change the chemical profile of the SiGe layer.
What is needed is a method and process to form an improved poly SiGe deposition layer on STI oxide for connection with a base electrode and with a reduced number of discontinuities.